mirror of
https://github.com/MikaylaFischler/cc-mek-scada.git
synced 2024-08-30 18:22:34 +00:00
148 lines
4.9 KiB
Lua
148 lines
4.9 KiB
Lua
require("/initenv").init_env()
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local rsio = require("scada-common.rsio")
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local util = require("scada-common.util")
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local testutils = require("test.testutils")
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local IO = rsio.IO
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local IO_LVL = rsio.IO_LVL
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local IO_MODE = rsio.IO_MODE
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local print = util.print
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local println = util.println
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-- list of inverted digital signals<br>
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-- only using the key for a quick lookup, value just can't be nil
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local DIG_INV = {
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[IO.F_SCRAM] = 0,
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[IO.R_SCRAM] = 0,
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[IO.WASTE_PU] = 0,
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[IO.WASTE_PO] = 0,
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[IO.WASTE_POPL] = 0,
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[IO.WASTE_AM] = 0,
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[IO.U_EMER_COOL] = 0
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}
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println("starting RSIO tester")
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println("")
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println(">>> checking valid ports:")
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-- port function tests
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local cid = 0
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local max_value = 1
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for key, value in pairs(IO) do
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if value > max_value then max_value = value end
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cid = cid + 1
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local c_name = rsio.to_string(value)
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local io_mode = rsio.get_io_mode(value)
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local mode = ""
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if io_mode == IO_MODE.DIGITAL_IN then
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mode = " (DIGITAL_IN)"
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elseif io_mode == IO_MODE.DIGITAL_OUT then
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mode = " (DIGITAL_OUT)"
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elseif io_mode == IO_MODE.ANALOG_IN then
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mode = " (ANALOG_IN)"
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elseif io_mode == IO_MODE.ANALOG_OUT then
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mode = " (ANALOG_OUT)"
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else
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error("unknown mode for port " .. key)
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end
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assert(key == c_name, c_name .. " != " .. key .. ": " .. value .. mode)
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println(c_name .. ": " .. value .. mode)
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end
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assert(max_value == cid, "IO_PORT last IDx out-of-sync with count: " .. max_value .. " (count " .. cid .. ")")
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testutils.pause()
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println(">>> checking invalid ports:")
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testutils.test_func("rsio.to_string", rsio.to_string, { -1, 100, false }, "UNKNOWN")
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testutils.test_func_nil("rsio.to_string", rsio.to_string, "UNKNOWN")
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testutils.test_func("rsio.get_io_mode", rsio.get_io_mode, { -1, 100, false }, IO_MODE.ANALOG_IN)
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testutils.test_func_nil("rsio.get_io_mode", rsio.get_io_mode, IO_MODE.ANALOG_IN)
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testutils.pause()
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println(">>> checking validity checks:")
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local ivc_t_list = { 0, -1, 100 }
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testutils.test_func("rsio.is_valid_port", rsio.is_valid_port, ivc_t_list, false)
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testutils.test_func_nil("rsio.is_valid_port", rsio.is_valid_port, false)
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local ivs_t_list = rs.getSides()
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testutils.test_func("rsio.is_valid_side", rsio.is_valid_side, ivs_t_list, true)
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testutils.test_func("rsio.is_valid_side", rsio.is_valid_side, { "" }, false)
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testutils.test_func_nil("rsio.is_valid_side", rsio.is_valid_side, false)
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local ic_t_list = { colors.white, colors.purple, colors.blue, colors.cyan, colors.black }
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testutils.test_func("rsio.is_color", rsio.is_color, ic_t_list, true)
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testutils.test_func("rsio.is_color", rsio.is_color, { 0, 999999, colors.combine(colors.red, colors.blue, colors.black) }, false)
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testutils.test_func_nil("rsio.is_color", rsio.is_color, false)
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testutils.pause()
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println(">>> checking port-independent I/O wrappers:")
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testutils.test_func("rsio.digital_read", rsio.digital_read, { true, false }, { IO_LVL.HIGH, IO_LVL.LOW })
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print("rsio.analog_read(): ")
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assert(rsio.analog_read(0, 0, 100) == 0, "RS_READ_0_100")
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assert(rsio.analog_read(7.5, 0, 100) == 50, "RS_READ_7_5_100")
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assert(rsio.analog_read(15, 0, 100) == 100, "RS_READ_15_100")
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assert(rsio.analog_read(4, 0, 15) == 4, "RS_READ_4_15")
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assert(rsio.analog_read(12, 0, 15) == 12, "RS_READ_12_15")
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println("PASS")
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print("rsio.analog_write(): ")
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assert(rsio.analog_write(0, 0, 100) == 0, "RS_WRITE_0_100")
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assert(rsio.analog_write(100, 0, 100) == 15, "RS_WRITE_100_100")
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assert(rsio.analog_write(4, 0, 15) == 4, "RS_WRITE_4_15")
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assert(rsio.analog_write(12, 0, 15) == 12, "RS_WRITE_12_15")
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println("PASS")
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testutils.pause()
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println(">>> checking port I/O:")
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print("rsio.digital_is_active(...): ")
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-- check all digital ports
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for i = 1, rsio.NUM_PORTS do
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if rsio.get_io_mode(i) == IO_MODE.DIGITAL_IN or rsio.get_io_mode(i) == IO_MODE.DIGITAL_OUT then
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local high = DIG_INV[i] == nil
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assert(rsio.digital_is_active(i, IO_LVL.LOW) == not high, "IO_" .. rsio.to_string(i) .. "_LOW")
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assert(rsio.digital_is_active(i, IO_LVL.HIGH) == high, "IO_" .. rsio.to_string(i) .. "_HIGH")
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end
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end
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assert(rsio.digital_is_active(IO.F_MATRIX_CHG, IO_LVL.LOW) == nil, "ANA_DIG_READ_LOW")
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assert(rsio.digital_is_active(IO.F_MATRIX_CHG, IO_LVL.HIGH) == nil, "ANA_DIG_READ_HIGH")
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println("PASS")
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-- check digital write
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print("rsio.digital_write_active(...): ")
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-- check all digital ports
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for i = 1, rsio.NUM_PORTS do
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if rsio.get_io_mode(i) == IO_MODE.DIGITAL_IN or rsio.get_io_mode(i) == IO_MODE.DIGITAL_OUT then
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local high = DIG_INV[i] == nil
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assert(rsio.digital_write_active(i, not high) == IO_LVL.LOW, "IO_" .. rsio.to_string(i) .. "_LOW")
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assert(rsio.digital_write_active(i, high) == IO_LVL.HIGH, "IO_" .. rsio.to_string(i) .. "_HIGH")
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end
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end
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assert(rsio.digital_write_active(IO.F_MATRIX_CHG, true) == false, "ANA_DIG_WRITE_TRUE")
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assert(rsio.digital_write_active(IO.F_MATRIX_CHG, false) == false, "ANA_DIG_WRITE_FALSE")
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println("PASS")
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println("TEST COMPLETE")
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