Lincoln Stein c6dcbce043 make lineart controlnet processor use MM ram cache; move model locations into processor class files		2024-07-01 19:17:15 -04:00
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image_util	make lineart controlnet processor use MM ram cache; move model locations into processor class files	2024-07-01 19:17:15 -04:00
ip_adapter	Improve RAM<->VRAM memory copy performance in LoRA patching and elsewhere (#6490)	2024-06-13 17:10:03 +00:00
model_hash	Run ruff	2024-06-26 21:46:59 +10:00
model_manager	controlnet processors use MM cache system	2024-06-30 21:17:04 -04:00
onnx	Improve RAM<->VRAM memory copy performance in LoRA patching and elsewhere (#6490)	2024-06-13 17:10:03 +00:00
stable_diffusion	Fix handling of init_timestep in StableDiffusionGeneratorPipeline and improve its documentation.	2024-06-26 12:51:51 -04:00
tiles	feat(nodes): extract LATENT_SCALE_FACTOR to constants.py	2024-03-01 10:42:33 +11:00
util	fix(backend): mps should not use non_blocking	2024-06-27 19:15:23 +10:00
__init__.py	consolidate model manager parts into a single class	2024-03-01 10:42:33 +11:00
lora.py	fix(backend): mps should not use non_blocking	2024-06-27 19:15:23 +10:00
model_patcher.py	ruff format	2024-06-27 09:45:13 -04:00
raw_model.py	Improve RAM<->VRAM memory copy performance in LoRA patching and elsewhere (#6490)	2024-06-13 17:10:03 +00:00
textual_inversion.py	Improve RAM<->VRAM memory copy performance in LoRA patching and elsewhere (#6490)	2024-06-13 17:10:03 +00:00